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74alvt16600 2.5v/3.3v 18-bit universal bus transceiver (3-state) product specification replaces data of 1997 may 12 ic23 data handbook 1998 feb 13 integrated circuits
philips semiconductors product specification 74alvt16600 2.5v/3.3v 18-bit universal bus transceiver (3-state) 2 1998 feb 13 853-1979 18958 features ? 18-bit bidirectional bus interface ? 5v i/o compatible ? 3-state buffers ? output capability: +64ma/-32ma ? ttl input and output switching levels ? input and output interface capability to systems at 5v supply ? bus-hold data inputs eliminate the need for external pull-up resistors to hold unused inputs ? live insertion/extraction permitted ? power-up reset ? power-up 3-state ? no bus current loading when output is tied to 5v bus ? negative edge-triggered clock inputs ? latch-up protection exceeds 500ma per jedec jc40.2 std 17 ? esd protection exceeds 2000v per mil std 883 method 3015 and 200v per machine model description the 74alvt16600 is a high-performance bicmos product designed for v cc operation at 2.5v and 3.3v with i/o compatibility up to 5v. this device is an 18-bit universal transceiver featuring non-inverting 3-state bus compatible outputs in both send and receive directions. data flow in each direction is controlled by output enable (oeab and oeba ), latch enable (leab and leba), and clock (cpab and cpba ) inputs. for a-to-b data flow, the device operates in the transparent mode when leab is high. when leab is low, the a data is latched if cpab is held at a high or low logic level. if leab is low, the a-bus data is stored in the latch/flip-flop on the high-to-low transition of cpab . when oeab is low, the outputs are active. when oeab is high, the outputs are in the high-impedance state. the high clock can be controlled with the clock-enable inputs (ceba /ceab ). data flow for b-to-a is similar to that of a-to-b but uses oeba , leba and cpba . active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level. quick reference data symbol parameter conditions typical unit symbol parameter t amb = 25 c 2.5v 3.3v unit t plh t phl propagation delay an to bn or bn to an c l = 50pf 1.9 2.5 1.6 1.9 ns c in input capacitance dir, oe v i = 0v or v cc 4 4 pf c i/o i/o pin capacitance outputs disabled; v i/o = 0v or v cc 8 8 pf i ccz total supply current outputs disabled 40 70 m a ordering information packages temperature range outside north america north america dwg number 56-pin plastic ssop type iii 40 c to +85 c 74alvt16600 dl av16600 dl sot371-1 56-pin plastic tssop type ii 40 c to +85 c 74alvt16600 dgg av16600 dgg sot364-1 pin description pin number symbol name and function 1, 27 oeab /oeba a-to-b output enable input (active low) 29, 56 ceba /ceab b-to-a / a-to-b clock enable (active low) 2, 28 leab/leba a-to-b/b-to-a latch enable input 55,30 cpab /cpba a-to-b/b-to-a clock input (active falling edge) 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 a0-a17 data inputs/outputs (a side) 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 b0-b17 data inputs/outputs (b side) 4, 11, 18, 25, 32, 39, 46, 53 gnd ground (0v) 7, 22, 35, 50 v cc positive supply voltage
philips semiconductors product specification 74alvt16600 2.5v/3.3v 18-bit universal bus transceiver (3-state) 1998 feb 13 3 function table inputs output ceab oeab leab cpab a b x h x x x z x l h x l l x l h x h h h l l x x b o l l l l l l l l h h l l l h x b o l l l l x b o x =don't care h =high voltage level l = low voltage level =high-to-low clock transition 2 a-to-b data flow is shown: b-to-a flow is similar but uses oeba , leba, cpba , and ceba . output level before the indicated steady-state input conditions were established. output level before the indicated steady-state input conditions were established, provided that clkab was low before leab went low. pin configuration gnd gnd ceab gnd leab oeab gnd v cc v cc gnd gnd v cc v cc gnd ceba gnd leba oeba 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 a0 a1 a2 a3 a4 a5 a6 a7 a8 a9 a10 a11 a12 a13 a14 a15 a16 a17 cpab b0 b2 b1 b3 b4 b5 b6 b7 b8 b9 b10 b11 b12 b13 b14 b15 b16 b17 cpba sw00191
philips semiconductors product specification 74alvt16600 2.5v/3.3v 18-bit universal bus transceiver (3-state) 1998 feb 13 4 logic diagram (positive logic) ce id id ce oeab ceab cpab leab cpba leba 1 56 55 2 28 30 54 b0 to 17 other channels sw00190 ceba a0 oeba 29 27 3 c1 clk c1 clk absolute maximum ratings 1, 2 symbol parameter conditions rating unit v cc dc supply voltage 0.5 to +4.6 v i ik dc input diode current v i < 0 50 ma v i dc input voltage 3 0.5 to +7.0 v i ok dc output diode current v o < 0 50 ma v out dc output voltage 3 output in off or high state 0.5 to +7.0 v i o dc out p ut current output in low state 128 ma i out dc o u tp u t c u rrent output in high state 64 ma t stg storage temperature range 65 to +150 c notes: 1. stresses beyond those listed may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditionso is not implied. exposur e to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. the performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create ju nction temperatures which are detrimental to reliability. the maximum junction temperature of this integrated circuit should not excee d 150 c. 3. the input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
philips semiconductors product specification 74alvt16600 2.5v/3.3v 18-bit universal bus transceiver (3-state) 1998 feb 13 5 recommended operating conditions symbol parameter 2.5v range limits 3.3v range limits unit symbol parameter min max min max unit v cc dc supply voltage 2.3 2.7 3.0 3.6 v v i input voltage 0 5.5 0 5.5 v v ih high-level input voltage 1.7 2.0 v v il input voltage 0.7 0.8 v i oh high-level output current 8 32 ma i ol low-level output current 8 32 ma i ol low-level output current; current duty cycle 50%; f 1khz 24 64 ma d t/ d v input transition rise or fall rate; outputs enabled 10 10 ns/v t amb operating free-air temperature range 40 +85 40 +85 c dc electrical characteristics (3.3v 0.3v range) limits symbol parameter test conditions temp = -40 c to +85 c unit min typ 1 max v ik input clamp voltage v cc = 3.0v; i ik = 18ma 0.85 1.2 v v oh high-level out p ut voltage v cc = 3.0 to 3.6v; i oh = 100 m a v cc 0.2 v cc v v oh high - level out ut voltage v cc = 3.0v; i oh = 32ma 2.0 2.3 v v cc = 3.0v; i ol = 100 m a 0.07 0.2 v ol lowlevel output voltage v cc = 3.0v; i ol = 16ma 0.25 0.4 v v cc = 3.0v; i ol = 32ma 0.3 0.5 v cc = 3.0v; i ol = 64ma 0.4 0.55 v rst power-up output low voltage 6 v cc = 3.6v; i o = 1ma; v i = v cc or gnd 0.55 v v cc = 3.6v; v i = v cc or gnd control pins 0.1 1 v cc = 0 or 3.6v; v i = 5.5v 0.1 10 i i input leakage current v cc = 3.6v; v i = 5.5v 4 0.1 20 m a v cc = 3.6v; v i = v cc data pins 4 0.5 10 v cc = 3.6v; v i = 0v 0.1 -5 i off off current v cc = 0v; v i or v o = 0 to 4.5v 0.1 100 m a bus hold current v cc = 3v; v i = 0.8v 75 130 i hold bus hold current data in p uts 7 v cc = 3v; v i = 2.0v 75 140 m a data inputs 7 v cc = 0v to 3.6v; v cc = 3.6v 500 i ex current into an output in the high state when v o > v cc v o = 5.5v; v cc = 3.0v 10 125 m a i pu/pd power up/down 3-state output current 3 v cc 1.2v; v o = 0.5v to v cc ; v i = gnd or v cc oe = don't care 1.0 100 m a i cch v cc = 3.6v; outputs high, v i = gnd or v cc, i o = 0 0.06 0.1 i ccl quiescent supply current v cc = 3.6v; outputs low, v i = gnd or v cc, i o = 0 4.0 5 ma i ccz v cc = 3.6v; outputs disabled; v i = gnd or v cc, i o = 0 5 0.06 0.1 d i cc additional supply current per input pin 2 v cc = 3v to 3.6v; one input at v cc 0.6v, other inputs at v cc or gnd 0.04 0.4 ma notes: 1. all typical values are at v cc = 3.3v and t amb = 25 c. 2. this is the increase in supply current for each input at the specified voltage level other than v cc or gnd 3. this parameter is valid for any v cc between 0v and 1.2v with a transition time of up to 10msec. from v cc = 1.2v to v cc = 3.3v 0.3v a transition time of 100 m sec is permitted. this parameter is valid for t amb = 25 c only. 4. unused pins at v cc or gnd. 5. i ccz is measured with outputs pulled up to v cc or pulled down to ground. 6. for valid test results, data must not be loaded into the flip-flops (or latches) after applying power. 7. this is the bus hold overdrive current required to force the input to the opposite logic state.
philips semiconductors product specification 74alvt16600 2.5v/3.3v 18-bit universal bus transceiver (3-state) 1998 feb 13 6 ac characteristics (3.3v 0.3v range) gnd = 0v; t r = t f = 2.5ns; c l = 50pf; r l = 500 w ; t amb = 40 c to +85 c. limits symbol parameter waveform v cc = 3.3v 0.3v unit min typ 1 max f max maximum clock frequency 1 300 mhz t plh t phl propagation delay an to bn or bn to an 2 1.0 1.0 1.6 1.9 2.3 2.8 ns t plh t phl propagation delay clock low or high leab to bn or leba to an 3 1.5 1.5 2.2 2.5 3.3 4.2 ns t plh t phl propagation delay cpab to bn or cpba to an 1 1.5 1.5 2.6 3.2 4.2 4.8 ns t pzh t pzl output enable time to high and low level 5 6 1.5 1.0 2.2 1.6 3.4 2.6 ns t phz t plz output disable time from high and low level 5 6 1.5 1.5 2.6 2.3 3.8 3.5 ns note: 1. all typical values are at v cc = 3.3v and t amb = 25 c. ac setup requirements (3.3v 0.3v range) gnd = 0v; t r = t f = 2.5ns; c l = 50pf, r l = 500 w ; t amb = 40 c to +85 c. limits symbol parameter waveform v cc = 3.3v 0.3v unit min typ 1 ts(h) ts(l) setup time, high or low an to cpab or bn to cpba 4 2.0 2.0 0.8 0.9 ns th(h) th(l) hold time, high or low an to cpab or bn to cpba 4 0.0 0.0 0.9 0.7 ns ts(h) ts(l) setup time, high or low clock low an to leab or bn to cpba 4 1.0 1.0 0.4 0.1 ns th(h) th(l) hold time, high or low clock high an to leab or bn to leba 4 1.0 1.0 0.1 0.4 ns ts(h) ts(l) setup time ceab before cpab or ceba before cpba 4 1.5 1.0 0.3 0.6 ns th(h) th(l) hold time ceab after cpab or ceba after cpba 4 1.5 1.0 0.7 0.2 ns tw(h) tw(l) pulse width, high or low cpab or cpba 1 1.5 1.5 ns tw(h) leab or leba pulse width, high 3 1.5 ns note: 1. all typical values are at v cc = 3.3v and t amb = 25 c.
philips semiconductors product specification 74alvt16600 2.5v/3.3v 18-bit universal bus transceiver (3-state) 1998 feb 13 7 dc electrical characteristics (2.5v 0.2v range) limits symbol parameter test conditions temp = -40 c to +85 c unit min typ 1 max v ik input clamp voltage v cc = 2.3v; i ik = 18ma 0.85 1.2 v v oh high-level out p ut voltage v cc = 2.3 to 3.6v; i oh = 100 m a v cc 0.2 v v oh high - level out ut voltage v cc = 2.3v; i oh = 8ma 1.8 v v cc = 2.3v; i ol = 100 m a 0.07 0.2 v ol low-level output voltage v cc = 2.3v; i ol = 24ma 0.3 0.5 v v cc = 2.3v; i ol = 8ma 0.4 v rst power-up output low voltage 7 v cc = 2.7v; i o = 1ma; v i = v cc or gnd 0.55 v v cc = 2.7v; v i = v cc or gnd control pins 0.1 1 v cc = 0 or 2.7v; v i = 5.5v 0.1 10 i i input leakage current v cc = 2.7v; v i = 5.5v 4 0.1 20 m a v cc = 2.7v; v i = v cc data pins 4 0.1 1 v cc = 2.7v; v i = 0 0.1 -5 i off off current v cc = 0v; v i or v o = 0 to 4.5v 0.1 100 m a i h o ld bus hold current v cc = 2.3v; v i = 0.7v 90 m a hold data inputs 6 v cc = 2.3v; v i = 1.7v 75 m a i ex current into an output in the high state when v o > v cc v o = 5.5v; v cc = 2.3v 10 125 m a i pu/pd power up/down 3-state output current 3 v cc 1.2v; v o = 0.5v to v cc ; v i = gnd or v cc ; oe = don't care 1 100 m a i cch v cc = 2.7v; outputs high, v i = gnd or v cc, i o = 0 0.04 0.1 i ccl quiescent supply current v cc = 2.7v; outputs low, v i = gnd or v cc, i o = 0 3.0 4.5 ma i ccz v cc = 2.7v; outputs disabled; v i = gnd or v cc, i o = 0 5 0.04 0.1 d i cc additional supply current per input pin 2 v cc = 2.3v to 2.7v; one input at v cc 0.6v, other inputs at v cc or gnd 0.01 0.4 ma notes: 1. all typical values are at v cc = 2.5v and t amb = 25 c. 2. this is the increase in supply current for each input at the specified voltage level other than v cc or gnd 3. this parameter is valid for any v cc between 0v and 1.2v with a transition time of up to 10msec. from v cc = 1.2v to v cc = 2.5v 0.2v a transition time of 100 m sec is permitted. this parameter is valid for t amb = 25 c only. 4. unused pins at v cc or gnd. 5. i ccz is measured with outputs pulled up to v cc or pulled down to ground. 6. not guaranteed. 7. for valid test results, data must not be loaded into the flip-flops (or latches) after applying power.
philips semiconductors product specification 74alvt16600 2.5v/3.3v 18-bit universal bus transceiver (3-state) 1998 feb 13 8 ac characteristics (2.5v 0.2v range) gnd = 0v; t r = t f = 2.5ns; c l = 50pf; r l = 500 w ; t amb = 40 c to +85 c. limits symbol parameter waveform v cc = 2.5v 0.2v unit min typ 1 max f max maximum clock frequency 1 250 mhz t plh t phl propagation delay an to bn or bn to an 2 1.0 1.5 1.9 2.5 3.0 3.6 ns t plh t phl propagation delay clock low or high leab to bn or leba to an 3 2.0 2.5 3.0 3.3 4.5 5.1 ns t plh t phl propagation delay cpab to bn or cpba to an 1 2.5 2.5 3.8 4.5 5.6 6.7 ns t pzh t pzl output enable time to high and low level 5 6 2.0 1.0 3.1 2.0 4.4 3.0 ns t phz t plz output disable time from high and low level 5 6 1.5 1.5 2.5 2.3 4.1 3.6 ns note: 1. all typical values are at v cc = 3.3v and t amb = 25 c. ac setup requirements (2.5v 0.2v range) gnd = 0v; t r = t f = 2.5ns; c l = 50pf, r l = 500 w ; t amb = 40 c to +85 c. limits symbol parameter waveform v cc = 2.5v 0.2v unit min typ 1 ts(h) ts(l) setup time, high or low an to cpab or bn to cpba 4 1.5 2.0 0.5 1.1 ns th(h) th(l) hold time, high or low an to cpab or bn to cpba 4 0.0 1.0 1.1 0.4 ns ts(h) ts(l) setup time, high or low clock low an to leab or bn to cpba 4 0.0 1.5 0.8 0.4 ns th(h) th(l) hold time, high or low clock high an to leab or bn to leba 4 1.0 1.5 0.4 0.9 ns ts(h) ts(l) setup time ceab before cpab or ceba before cpba 4 1.0 1.0 0.3 0.5 ns th(h) th(l) hold time ceab after cpab or ceba after cpba 4 1.5 1.5 0.8 0.5 ns tw(h) tw(l) pulse width, high or low cpab or cpba 1 2.5 2.5 ns tw(h) leab or leba pulse width, high 3 1.5 ns note: 1. all typical values are at v cc = 2.5v and t amb = 25 c.
philips semiconductors product specification 74alvt16600 2.5v/3.3v 18-bit universal bus transceiver (3-state) 1998 feb 13 9 ac waveforms notes: 1. v m = 1.5v at v cc 3.0v, v m = v cc /2 at v cc 2.7v 2. v x = v ol + 0.3v at v cc 3.0v, v x = v ol + 0.15v at v cc 2.7v 3. v y = v oh 0.3v at v cc 3.0v, v y = v oh 0.15v at v cc 2.7v t phl t plh v m v oh t w (l) 1/f max cpba or cpab an or bn t w (h) sw00038 v m v m v m v ol 3.0v or v cc , whichever is less 0v waveform 1. propagation delay, clock input to output, clock pulse width, and maximum clock frequency v ol t plh v oh 0v an or bn an or bn v m v m t phl v m v m sw00176 3.0v or v cc , whichever is less waveform 2. propagation delay, transparent mode t plh t phl t w (h) v m v m v m v m v m leab or leba an or bn 0v v oh v ol sw00177 3.0v or v cc , whichever is less waveform 3. propagation delay, enable to output, and enable pulse width v m v m v m v m v m v m 3.0v or v cc whichever is less 0v na x , nb x ceab ceba leab or leba t s (h) t h (h) t s (l) t h (l) 0v cpab or cpba 3.0v or v cc whichever is less sw00271 or waveform 4. data setup and hold times oeba or oeab an or bn t pzh t phz v oh v y v m v m v m 3.0v or v cc , whichever is less 0v 0v sw00270 waveform 5. 3-state output enable time to high level and output disable time from high level oeba or oeab t pzl t plz an or bn v x v m v m v m 3.0v or v cc , whichever is less 3.0v or v cc 0v v ol sw00269 waveform 6. 3-state output enable time to low level and output disable time from low level
philips semiconductors product specification 74alvt16600 2.5v/3.3v 18-bit universal bus transceiver (3-state) 1998 feb 13 10 test circuit and waveforms pulse generator v in v out c l v cc r l test circuit for 3-state outputs v m v m t w negative pulse 10% 10% 90% 90% 0v v m v m t w positive pulse 90% 90% 10% 10% 0v t thl (t f ) t tlh (t r )t thl (t f ) t tlh (t r ) definitions r l = load resistor; see ac characteristics for value. c l = load capacitance includes jig and probe capacitance: see ac characteristics for value. r t = termination resistance should be equal to z out of pulse generators. input pulse requirements family 74alvt16 switch position test switch t plz/ t pzl 6v or v cc x 2 t plh/ t phl open t phz /t pzh gnd 6.0v or v cc x 2 r t r l open gnd sw00025 d.u.t. amplitude rep. rate t w t r t f 3.0v or v cc whichever is less 10mhz 500ns 2.5ns 2.5ns v in v in
philips semiconductors product specification 74alvt16600 2.5v/3.3v 18-bit universal bus transceiver (3-state) 1998 feb 13 11 ssop56: plastic shrink small outline package; 56 leads; body width 7.5 mm sot371-1
philips semiconductors product specification 74alvt16600 2.5v/3.3v 18-bit universal bus transceiver (3-state) 1998 feb 13 12 tssop56: plastic thin shrink small outline package; 56 leads; body width 6.1mm sot364-1
philips semiconductors product specification 74alvt16600 2.5v/3.3v 18-bit universal bus transceiver (3-state) 1998 feb 13 13 notes
philips semiconductors product specification 74alvt16600 2.5v/3.3v 18-bit universal bus transceiver (3-state) yyyy mmm dd 14 definitions short-form specification e the data in a short-form specification is extracted from a full data sheet with the same type number and title. for detailed information see the relevant data sheet or data handbook. limiting values definition e limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the dev ice at these or at any other conditions above those given in the characteristics sections of the specification is not implied. exposure to limi ting values for extended periods may affect device reliability. application information e applications that are described herein for any of these products are for illustrative purposes only. philips semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. disclaimers life support e these products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. philips semiconductors customers using or selling these products for use i n such applications do so at their own risk and agree to fully indemnify philips semiconductors for any damages resulting from such application. right to make changes e philips semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. philips semiconductors ass umes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or m ask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right in fringement, unless otherwise specified. philips semiconductors 811 east arques avenue p.o. box 3409 sunnyvale, california 940883409 telephone 800-234-7381 ? copyright philips electronics north america corporation 1998 all rights reserved. printed in u.s.a. print code date of release: 05-96 document order number: 9397-750-03569
data sheet status objective specification preliminary specification product specification product status development qualification production definition [1] this data sheet contains the design target or goal specifications for product development. specification may change in any manner without notice. this data sheet contains preliminary data, and supplementary data will be published at a later date. philips semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. this data sheet contains final specifications. philips semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. data sheet status [1] please consult the most recently issued datasheet before initiating or completing a design.

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